Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit

ABSTRACT

A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

BACKGROUND OF INVENTION

[0001] 1. Field of the Inventionbk2E001200303263

[0002] The present invention relates to a switched capacitor circuit,and more particularly, to a switched capacitor circuit used in a voltagecontrolled oscillator (VCO) that can minimize the clock feedthrougheffect thereby preventing the VCO frequency drift phenomenon duringcalibration and the synthesizer phase locking period.

[0003] 2. Description of the Prior Art

[0004] A voltage controlled oscillator (VCO) is commonly used forfrequency synthesis in wireless communication circuits. As Welland, etal. state in U.S. Pat. No. 6,226,506, wireless communication systemstypically require frequency synthesis in both the receive path circuitryand the transmit path circuitry.

[0005]FIG. 1 shows a VCO circuit according to the prior art. An LC typeVCO 10 used in a frequency synthesizer contains aresonator, the basicresonant structure includes an inductor 12 connected between a firstoscillator node OSC_P and a second oscillator node OSC_N. Connected inparallel with the inductor 12 is a continuously variable capacitor 14and a plurality of discretely variable capacitors 16. The continuouslyvariable capacitor 14 is used for fine-tuning a desired capacitancewhile the plurality of discretely variable capacitors 16 is used forcoarse tuning. The resistive loss of the parallel combination ofinductor and capacitors is compensated by a negative resistancegenerator 18 to sustain the oscillation.

[0006] Each discretely variable capacitor in the plurality of discretelyvariable capacitors 16 is made up of a switched capacitor circuit 20 andeach switched capacitor circuit is controlled by an independent controlsignal 22.

[0007] Based on this control signal 22 the switched capacitor circuit 20can selectively connect or disconnect a capacitor 24 to the resonator ofthe VCO 10. Different on/off combinations of switched capacitor arraysresults in a wider capacitance range of the LC type resonator and hencea wider VCO 10 oscillation frequency coverage.

[0008]FIG. 2 shows a switched capacitor circuit 20 a according to theprior art. A capacitor 30 is connected between the first oscillator nodeOSC_P and a node A. A switch element 32 selectively connects node A toground, and the switch element 32 is controlled by a control signal SW.When the switch element 32 is turned on, the capacitance associated withthe capacitor 30 is added to the overall capacitance in the VCO 10resonator. When the switch element 32 is turned off, the capacitancelooking into the first oscillator node OSC_P is the series combinationof the capacitor 30 and the off state capacitance associated with theswitch element 32.

[0009]FIG. 3 shows a differential type switched capacitor circuit 20 baccording to the prior art. Differential implementations have muchgreater common-mode noise rejection and are widely used in high-speedintegrated circuit environments. In the differential switched capacitorcircuit 20 b, a positive side capacitor 40 is connected between thefirst oscillator node OSC_P and a node A. A positive side switch element42 selectively connects node A to ground. A negative side capacitor 44is connected between the second oscillator node OSC_N and a node B. Anegative side switch element 46 selectively connects node B to ground.There is also a center switch element 48 used to lower the overallturn-on switch resistance connected between node A and node B. All threeswitch elements 42, 46, 48 are controlled by the same control signal SW.When the switch elements 42, 46, 48 are turned on, the capacitanceassociated with the series combination of the positive and negative sidecapacitors 40, 44 is added to the overall capacitance in the VCO 10.When the switch elements 42, 46, 48 are turned off, the differentialinput capacitance is the series combination of the positive and negativeside capacitors 40, 44 and other switch parasitic capacitance. Theoverall input capacitance when all switch elements 42, 46, 48 are turnedoff is lower than that when all switch elements 42, 46, 48 are turnedon. Without the center switch element 48, the switched capacitor circuit20 b is itself another embodiment of the differential type switchcapacitor circuit according to the prior art.

[0010] Regardless of whether the single ended implementation shown inFIG. 2 or the differential implementation shown in FIG. 3 is used, whenthe switched capacitor circuit 20 a or 20 b is turned off, a momentaryvoltage step change occurs at node A (and in the case of thedifferential implementation shown in FIG. 3 also at node B). Themomentary voltage step causes an undesired change in the overallcapacitance, and ultimately, an undesired change in the VCO 10frequency. This momentary voltage step change in FIG. 2 and FIG. 3, byusing NMOS switches, is a voltage drop when the switch elements 32, 42,46, 48 are turned off.

[0011] Using the single ended case shown in FIG. 2 as an example, whenthe switch element 32 is turned off, charge carriers are injected to thejunction capacitance connected between the first terminal and the secondterminal of the switch element 32. The injection produces an undesiredvoltage step change across the capacitive impedance and appears as avoltage drop at node A. This effect is known as clock feedthrough effectand appears as a feedthrough of the control signal SW from the controlterminal of the switch element 32 to the first and second terminals ofthe switch element 32. When the switch element 32 is turned on, node Ais connected to ground so the feedthrough of the control signal SW is ofno consequence. However, when the switch element 32 is turned off, thefeedthrough of the control signal SW causes a voltage step, in the forma voltage drop to appear at node A. Because of the dropped voltage atnode A, the diode formed by the N³⁰ diffusion of switch element 32 andthe P type substrate in the off state will be slightly forward biased.The voltage level at node A will spike low and then recover to groundpotential as the forward biased junction diode formed by the switchelement 32 in the off state allows current to flow. The voltage drop andrecovery at node A changes the load capacitance of the VCO 10 resonatorand causes an undesired momentarily drift in the VCO 10 frequency.

[0012] When the differential switched capacitor circuit 20 b shown inFIG. 3 switches off, it suffers from the same clock feedthrough effectproblem at node A and at node B. The positive side node A has anundesired voltage step change caused by the clock feedthrough effect ofboth the positive side switch element 42 and the clock feedthrougheffect of the center switch element 48. Similarly, the negative sidenode B has an undesired voltage step caused by the clock feedthrougheffect of both the negative side switch element 46 and the clockfeedthrough effect of the center switch element 48. The voltage stepchange and recovery at node A and node B changes the capacitance of theVCO 10 resonator and causes an undesired momentary drift in the VCO 10frequency.

SUMMARY OF INVENTION

[0013] It is therefore a primary objective of the present invention toprovide a switched capacitor circuit capable of minimizing the clockfeedthrough effect, to solve the above-mentioned problem.

[0014] According to the present invention, a switched capacitor circuitcapable of minimizing clock feedthrough effect. The switched capacitorcircuit comprising a switch element having a first terminal connected toa capacitor, a second terminal connected to ground, and a controlterminal; and a low-pass filter having an input terminal connected to acontrol signal and an output terminal connected to the control terminalof the switch element, wherein the low-pass filter is for making theswitch element gradually switch off.

[0015] According to the present invention, a switched capacitor circuitcapable of minimizing clock feedthrough effect, comprising a pluralityof differently sized switch elements for selectively connecting acapacitor to a node depending upon a control signal applied to a controlterminal of each of the switch elements. A sequence controller having aplurality of control signal outputs for switching off the switchelements in the plurality of differently sized pull down switch elementsin sequence based on decreasing order of switch size. The switchedcapacitor circuit further comprising a means for making the smallestswitch elements gradually switch off.

[0016] According to the present invention, a method for minimizing clockfeedthrough effect when switching a switched capacitor circuit. Themethod comprises providing a plurality of differently sized switchelements that selectively connect a capacitor to a node depending upon acontrol signal applied to a control terminal of each of the switchelements. When switching the switched capacitor circuit to an off state,sequencing the control signals such that the switch elements areswitched off in decreasing order based on size, whereby the largestswitch element is switched off first and the smallest switch element isswitched off last. The method further comprising when switching theswitched capacitor circuit to an off state, providing a means for makingthe smallest switch element gradually switch off.

[0017] It is a further advantage of the present invention that theswitched capacitor circuit is gradually switched off to minimize theclock feedthrough effect and prevent an undesired drift in the VCO 10frequency. In the prior art, the switched capacitor circuit is instantlyswitched from an on state to an off state. The clock feedthrough effectin the prior art implementations causes an undesired voltage step changeto slightly forward bias the junction diode formed by the switch elementin the off state until the voltage potential has returned to ground.

[0018] These and other objectives of the claimed invention will no doubtbecome obvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0019]FIG. 1 is a schematic diagram of a typical Voltage ControlledOscillator (VCO) circuit used in a frequency synthesizer according tothe prior art.

[0020]FIG. 2 shows a switched capacitor circuit used in the VCO of FIG.1 according to the prior art.

[0021]FIG. 3 shows a differential type switched capacitor circuit usedin the VCO of FIG. 1 according to the prior art.

[0022]FIG. 4 shows a switched capacitor circuit according to the firstembodiment of the present invention.

[0023]FIG. 5 shows a time domain plot of the control signals for theswitched capacitor circuit of FIG. 4

[0024]FIG. 6 shows a differential switched capacitor circuit accordingto the second embodiment of the present invention.

[0025]FIG. 7 shows a time domain plot of the control signals for thedifferential switched capacitor circuit of FIG. 6.

[0026]FIG. 8 shows an example switched capacitor circuit according tothe third embodiment of the present invention.

[0027]FIG. 9 shows a time domain plot of the present invention controlsignals for switching off the switched capacitor circuit of FIG. 8

[0028]FIG. 10 shows a generalized switched capacitor circuit of FIG. 8with a low-pass filter added to the control terminal of the smallestswitch element.

[0029]FIG. 11 shows a differential switched capacitor circuit accordingto the fourth embodiment of the present invention.

[0030]FIG. 12 shows a time domain plot of the present invention controlsignals for switching off the differential switched capacitor circuit ofFIG. 11.

[0031]FIG. 13 shows a generalized differential switched capacitorcircuit of FIG. 11 with a low-pass filter added to the control terminalof the smallest pull down switch element at the positive side and itscorresponding pull down switch element at the negative side.

[0032]FIG. 14 shows a method flowchart for minimizing clock feedthrougheffect when switching off a switched capacitor circuit according to thepresent invention.

[0033]FIG. 15 shows a method flowchart for minimizing clock feedthrougheffect when switching off a differential switched capacitor circuitaccording to the present invention.

DETAILED DESCRIPTION

[0034]FIG. 4 shows a switched capacitor circuit 20 c according to thefirst embodiment of the present invention. In the first embodiment, theswitched capacitor circuit 20 c comprises a capacitor 50, a switchelement 52, and a low-pass filter 54. The capacitor 50 is connectedbetween the first oscillator node OSC_P and a node A. Depending on thecontrol signal SW, the switch element 52 selectively connects the node Ato ground. When the switch element 52 is turned on, the capacitanceassociated with the capacitor 50 is added to the overall capacitance inthe VCO 10. When the switch element 52 is turned off, the capacitancelooking into the first oscillator node OSC_P is the series combinationof the capacitor 50 and the off state capacitance associated with theswitch element 32. A low-pass filter 54 is connected to a controlterminal of the switch element 52 for making the switch element 52gradually switch off.

[0035]FIG. 5 is a time domain plot of the control signal SW before thelow-pass filter 54 and a signal SW_FILTER after the low-pass filter 54.At time t₁ the control signal SW changes to a logic low. The low-passfilter 54 causes the signal SW_FILTER at the control terminal of theswitch element 52 to gradually change from a logic high to a logic lowand minimizes the voltage step change seen at node A. Because the switchelement 52 is gradually switched off, node A is gradually disconnectedfrom ground. As the switch element 52 is gradually switched off, duringa period of delay time there exists a conduction path of the switchelement, even with an increasing resistance, to ground to minimize theclock feedthrough effect. In contrast to the prior art, the presentinvention does not forward bias the diode formed by the switch element52 in the off state. The clock feedthrough effect at each moment in timeis reduced.

[0036]FIG. 6 shows a differential switched capacitor circuit 20 daccording to the second embodiment of the present invention. A positiveside capacitor 60 is connected between the first oscillator node OSC_Pand a node A. A positive side switch element 62 selectively connectsnode A to ground. A negative side capacitor 64 is connected between thesecond oscillator node OSC_N and a node B. A negative side switchelement 66 selectively connects node B to ground. A center switchelement 68 is used to lower the overall turn-on resistance and isconnected between node A and node B. A low-pass filter 70 is connectedto the control terminals of the positive side switch element 62 and thenegative side switch element 66 for making the positive and negativeside switch elements 62, 66 gradually switch off. Without the centerswitch element 68, the switched capacitor circuit 20 d is itself anotherembodiment of the differential type switched capacitor circuit.

[0037]FIG. 7 is a time domain plot of the control signal SW before thelow-pass filter and the signal SW_FILTER after the low-pass filter. Thecenter switch element 68 is directly controlled by the control signal SWwhile the positive and negative side switch elements 62, 66 arecontrolled by the output of the low-pass filter 70, signal SW_FITLER. Attime t₁ the control signal SW changes from a logic high to a logic lowand the center switch element 68 immediately changes to an off state.Because the positive and negative side switch elements 62, 66 graduallyswitch off, during a period of delay time, node A and node B are stillconnected to ground and the clock feedthrough effect due to the centerswitch element 68 is minimized by the conduction to ground path. As inthe single ended embodiment of FIG. 4, as the positive and negative sideswitch elements 62, 66 gradually switch off, the clock feedthrougheffect produced at node A and B at each moment of time is reduced.

[0038]FIG. 8 shows an example of the switched capacitor circuit 20 eaccording to the third embodiment of the present invention. In the thirdembodiment, the switched capacitor circuit 20 e comprises a capacitor80, a sequence controller 88, and a plurality of differently sizedswitch elements 82. FIG. 8 shows two switch elements 84, 86 but this ismeant as an example only and more switch elements could be used. In thisexample, switch element 84 is larger than switch element 86. Thecapacitor 80 is connected between the first oscillator node OSC_P and anode A. Each of the switch elements 84, 86 in the plurality ofdifferently sized switch elements 82 selectively connects node A toground, and each switch element 84, 86 in the plurality of differentlysized switch elements 82 has its own control signal. In this example thelarger switch element 84 has a control signal SW1 and the smaller switchelement 86 has a control signal SW2.

[0039]FIG. 9 shows a time domain plot of the control signals of thepresent invention method for switching off the switched capacitorcircuit 20 e as shown in FIG. 8. In order to gradually switch theswitched capacitor circuit 20 e to an off state, the sequence controller88 ensures that the switch elements 84, 86 are switched off indecreasing order based on switch size. Because switch element 84 islarger than switch element 86, switch element 84 is first switched offat time t₁. At time t₂, which is after t₁, switch element 86 is switchedoff. Since the amount of voltage change at node A due to the clockfeedthrough effect depends on the parasitic capacitance ratio of controlterminal to first terminal and first terminal to second terminalcapacitance, the smaller the control terminal to first terminalcapacitance the smaller the voltage change due to the feedthrough of thecontrol signal switching from high to low. The present invention takesadvantage of this fact because the larger switch elements with largervoltage drops due to turning off the larger switch elements are switchedoff first. Until the last switch element is switched off, node A isconnected to ground and clock feedthrough effect is not a concern. Ifthe last switch element to be switched off is made sufficiently small,the clock feedthrough effect after the last switch is switched off canbe made negligible.

[0040]FIG. 10 shows a generalized third embodiment switched capacitorcircuit 20 f schematic. A capacitor 90 is connected between the firstoscillator node OSC_P and a node A. A plurality of differently sizedswitch elements 92 selectively connects node A to ground, and eachswitch element in the plurality of differently sized switch elements 92has its own control signal. A largest switch element Switch[1] has acontrol signal SW[1] and a size of W [1]. A smaller switch elementSwitch[2] has a control signal SW[2] and a size of W[2], where W[2] issmaller than W[1]. A second smallest switch element Switch[N-1] has acontrol signal SW[N-1] and a size of W[N-1], where W[N-1] is smallerthan W[N-2]. A smallest switch element Switch[N] has a control signalSW[N] and a size of W[N], where W[N] is smaller than W[N-1]. A sequencecontroller 96 provides the control signals SW[1] to SW[N] and ensuresthat the switch elements are switched off in decreasing order based onswitch size. As shown in FIG. 10, a low-pass filter 94 can be added, ornot added, to the control terminal the smallest switch elementSwitch[N]. Similar to the circuit shown in FIG. 4, the low-pass filter94 will gradually shut off the last switch element Switch[N] minimizingthe clock feedthrough effect of the switched capacitor circuit 20 f.

[0041]FIG. 11 shows an example of the differential switched capacitorcircuit 20 g according to the fourth embodiment of the presentinvention. The differential switched capacitor circuit 20 g comprises apositive side capacitor 100, a negative side capacitor 102, a centerswitch element 104, a sequence controller 116, a plurality ofdifferently sized positive side switch elements 106, and for each switchelement in the plurality of the differently sized positive side switchelements 106, a corresponding negative side switch element havingsubstantially the same size as the positive side switch element. FIG. 11shows two positive side switch elements 108, 110 and two correspondingnegative side switch elements 112, 114 but this is meant as an exampleonly and more switch elements could be used. In this example, switchelements 108 and 112 are of substantially the same size and are largerthan switch elements 110 and 114, which are also of substantially thesame size. The positive side capacitor 100 is connected between thefirst oscillator node OSC_P and a node A. Each of the switch elements108, 110 in the plurality of differently sized positive side switchelements 106 selectively connects node A to ground and each switchelement in the plurality of differently sized positive side switchelements 106 has its own control signal. The negative side capacitor 102is connected between the second oscillator node OSC_N and a node B. NodeB is selectively connected to ground by each of the correspondingnegative side switch elements 112, 114 depending on the control signalof the positive side switch element 108, 110 respectively. In thisexample, the larger switch elements 108, 112 have a control signal SW1and the smaller switch elements 110, 114 have a control signal SW2.Without the center switch element 104, the switched capacitor circuit 20g is itself another embodiment of the differential type switchedcapacitor circuit.

[0042]FIG. 12 shows a time domain plot of the control signals of thepresent invention method for switching off the forth embodiment of theswitched capacitor circuit 20 g as shown in FIG. 11. In order togradually switch the switched capacitor circuit 20 g to an off state,the sequence controller 116 ensures that the center switch element 104is first switched off (at time t₁) and then the remaining switchelements are switched off in pairs in decreasing order based on switchsize. At t₂, which is after t₁, switch elements 108 and 112 are switchedoff. At t₃, which is after t₂, switch elements 110 and 114 are switchedoff. Because the positive side switch element 108 and its correspondingnegative side switch element 112 are larger in size than the positiveside switch element 110 and its corresponding negative side switchelement 114, the positive side switch element 108 and the negative sideswitch element 112 are switched off next. Until the last positive andnegative side switch elements 110, 114 are switched off, node A and nodeB are connected to ground and clock feedthrough effect is not a concern.If the last switch element pair to be switched off is made sufficientlysmall, the clock feedthrough effect of the differential switch circuit20 g can be made negligible.

[0043]FIG. 13 shows a generalized fourth embodiment differentialswitched capacitor circuit 20 h. A positive side capacitor 120 isconnected between the first oscillator node OSC_P and a node A. Aplurality of differently sized positive side switch elements 122selectively connects node A to ground and each switch element in theplurality of differently sized positive side switch elements 122 has itsown control signal. A largest positive side switch element P_Switch[1]has a control signal SW[1] and a size of W[1]. A smaller positive sideswitch element P_Switch[2] has a control signal SW[2] and a size ofW[2], where W[2] is smaller than W[1]. A second smallest positive sideswitch element P_Switch[N-1] has a control signal SW[N-1] and a size ofW[N-1], where W[N-1] is smaller than W[N-2]. A smallest positive sideswitch element P_Switch[N] has a control signal SW[N] and a size of W[N], where W[N] is smaller than W[N-1]. For each switch element in theplurality of the differently sized positive side switch elements 122, acorresponding negative side switch element having substantially the samesize as the positive side switch element selectively connects a node Bto ground depending on the same control signal as the positive sideswitch element. A largest negative side switch element N_Switch[1] hasthe control signal SW[1] and the size of W[1]. A smaller negative sideswitch element N_Switch[2] has the control signal SW[2] and the size ofW[2]. A second smallest negative side switch element N_Switch[N-1] hasthe control signal SW[N-1] and the size of W[N-1]. A smallest negativeside switch element N_Switch[N] has the control signal SW[N] and a sizeof W[N]. A negative side capacitor 124 is connected between node B andthe second oscillator node OSC_N. A center switch element 126selectively connects node A to node B depending on a control signalSW_CENTER. A low-pass filter 128 can be connected, or not connected, tothe control terminals for the smallest switch element pair. Similar tothe circuit in FIG. 6, the low-pass filter 128 will gradually shut offthe last switch element pair P_Switch[N], N_Switch[N] minimizing theclock feedthrough effect of the differential switched capacitor circuit20 h. A sequence controller 130 provides the control signals SW_CENTERand SW[1] to SW[N] and ensures that the center switch element is firstswitched off and then the remaining switch elements are switched off inpairs in decreasing order based on switch size. Without the centerswitch element 126, the switched capacitor circuit 30 h is itselfanother embodiment of the differential type switched capacitor circuit.

[0044]FIG. 14 shows a method flowchart 198 for minimizing clockfeedthrough effect when switching off a switched capacitor circuit 20according to the present invention. The method flowchart 198 containsthe following steps:

[0045] Step 200: Provide a plurality of differently sized switchelements: Each switch element in the plurality of differently sizedswitch elements is for selectively connecting a first terminal of acapacitor to a node depending upon a control signal applied to a controlterminal of the switch element.

[0046] Step 202: Provide a low-pass filter to gradually switch off thesmallest switch element: The low-pass filter is connected to the controlterminal of the smallest switch element.

[0047] Step 204: When switching off, sequence the control signals suchthat the switch elements are switched off in decreasing order based onsize: The largest switch element is switched off first, the next largestis switched off next, and so on until the smallest switch element isswitched off last. Until the smallest switch element is switched off,the first terminal of the capacitor is connected to the node and theclock feedthrough effect is not a concern. The low-pass filter willgradually switch off the last switch element minimizing the clockfeedthrough effect of the smallest switch element and the switchedcapacitor circuit 20 as a whole.

[0048] It should be noted that in the method flowchart 198 shown in FIG.14 the node is preferably connected to ground, however, the methodaccording to the present invention is not limited to this configuration.

[0049]FIG. 15 shows a method flowchart 208 for minimizing clockfeedthrough effect when switching off a differential switched capacitorcircuit 20 according to the present invention. The method flowchart 208contains the following steps:

[0050] Step 210: Provide a plurality of differently sized positive sideswitch elements: Each positive side switch element in the plurality ofdifferently sized positive side switch elements is for selectivelyconnecting a first terminal of a positive side capacitor to a first nodedepending upon a control signal applied to a control terminal of each ofthe switch elements.

[0051] Step 212: For each positive side switch element, provide acorresponding same size negative side switch element: Each correspondingsame size negative side switch element is for selectively connecting afirst terminal of a negative side capacitor to a second node dependingupon the control signal applied to the control terminal of the positiveside switch element.

[0052] Step 214: Provide a low-pass filter to gradually switch off thesmallest positive and negative side switch elements: The low-pass filteris connected to the control terminal of the smallest positive andnegative side switch element.

[0053] Step 216: Provide a center switch element: The center switchelement selectively connects the positive side capacitor to the negativeside capacitor depending on a control signal applied to a controlterminal of the center switch element.

[0054] Step 218: When switching off, sequence the control signals suchthat the center switch element is first switched off and then the otherswitch elements are switched off in pairs in decreasing order based onswitch size, whereby the largest positive side switch element and itscorresponding negative side switch element are switched off first, thenext largest switch element pair is switch off next, and the smallestswitch element pair is switched off last. Until the smallest switchelement pair is switched off, the first terminal of the positive sidecapacitor and the first terminal of the negative side capacitor areconnected to the first node and the second respectively so that theclock feedthrough effect is not a concern. The low-pass filter graduallyswitches off the last switch element minimizing the clock feedthrougheffect of the smallest switch element and the switched capacitor circuit20 as a whole.

[0055] Similarly, it should be noted that in the method flowchart 208shown in FIG. 15 the first node and the second node are preferablyconnected to ground, however,the method according to the presentinvention is not limited to this configuration.

[0056] In contrast to the prior art, the present invention graduallyswitches off the switched capacitor circuit so that the clockfeedthrough effect is minimized and accordingly the undesired frequencydrift of the VCO 10 frequency is properly reduced. When switching off,the prior art implementations suffer from clock feedthrough effect thatcauses a voltage step change to occur at an internal capacitive node ofthe VCO 10. The voltage step change causes the junction diode formed bya switch element in the off state to be slightly forward biased untilthe dropped voltage returns to the ground potential.

[0057] According to the present invention, the voltage step change atthe internal capacitive node is minimized. When switching off, thepresent invention can minimize the momentary change of the capacitancevalue of the VCO 10 resonator and the momentary drift in the VCO 10frequency.

[0058] Those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teachings of the invention. Accordingly, that above disclosureshould be construed as limited only by the metes and bounds of theappended claims.

1. A switched capacitor circuit capable of minimizing clock feedthrougheffect, comprising: a positive side switch element for selectivelyconnecting a positive side first node to a positive side second nodedepending upon a signal applied to a first control terminal of thepositive side switch element, wherein the positive side first node isconnected to a positive side capacitor; and a low-pass filter having aninput terminal connected to a control signal and an output terminalconnected to the first control terminal of the positive side switchelement for making the positive side switch element gradually switch of,wherein the control signal is substantially a two-level signal with afirst level for switching off the switched capacitor circuit and asecond level for switching on the switched capacitor circuit.
 2. Theswitched capacitor circuit of claim 1, wherein the positive side secondnode is ground and the positive side switch element is an NMOStransistor.
 3. The switched capacitor circuit of claim 1, furthercomprising: a negative side switch element of substantially the samesize as the positive side switch element for selectively connecting anegative side first node to a negative side second node depending uponthe control signal applied to the first control terminal of the positiveside switch element, wherein the negative side first node is connectedto a negative side capacitor.
 4. The switched capacitor circuit of claim3, further comprising: a center switch element having a first terminalconnected to the positive side first node, a second terminal connectedto the negative side first node, and a third control terminal connectedto the control signal.
 5. The switched capacitor circuit of claim 4,wherein the positive side second node is ground, the negative sidesecond node is ground, and the positive side switch element, thenegative side switch element, and the center switch element are NMOStransistors. 6-24. (cancelled)